1. Field of the Invention
The present invention relates generally to the filed of semiconductor memory and, more particularly, to a 1-transistor, 1-resistor (1T1R) resistive memory device with vertical transistors and buried bit lines, and fabrication method thereof.
2. Description of the Prior Art
Current Flash and DRAM technologies are believed to scale down to 18 nm and face scaling limitations beyond 18 nm. Therefore, a variety of new memory schemes have been investigated. One of the most promising schemes is the resistive switching RAM or RRAM, which is operated based on the electronic (current or voltage induced) switching of a resistor element material between two stable resistive states.
One known form of a RRAM device has memory cells each built on a pillar diode structure. However, the equivalent circuit of each memory cell includes a tunnel gate surface effect transistor having non-uniform gate oxide built on the pillar diode structure. Thus, the pillar diode does not function as a diode in the forward conducting direction.
Another form of a resistive memory array utilizes FET access, which can be operated at relatively lower voltages and lower leakages. The resistive memory array utilizing the FET access also has better current control compared to the diode access RRAM. However, the fabrication process of such FET access RRAM is complex.
It is desirable to provide an improved resistive memory device with better scalability and an improved method for fabricating such device which is less complex than the prior art.